MIL-PRF-ATM (Advanced Technology Microcircuit) for SiP and MCM devices
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Introduction
- MIL-PRF-ATM (Advanced Technology Microcircuit) is intended to provide an avenue to introduce advanced packaged ICs with through silicon via (TSV) and other integration technologies into the Military and Space QML system
- MIL-PRF-ATM works alongside MIL-PRF-38535 (Integrated Circuits) and MIL-PRF-38534 (Hybrids) to ensure there is a path for EEE components using these integration methods to be included in the QML system
- Foundational elements from 38535 and 38534 are merged with OEM addressed degradation modes and mechanisms to provide a path to demonstrate technology capabilities and reliability for military and space usage
Scope of the MIL-PRF-ATM for SiP and MCM devices:
This specification establishes the general performance requirements for Advanced Technology Microcircuits (ATM) including the quality and reliability assurance requirements.
These requirements are intended to define and support appropriate requirements for ATM device acquisition. Multiple terms are used in industry and across standards development organizations (SDOs) for ATM and related devices.
These devices are primarily heterogeneous integrated (HI) products leveraging through silicon via (TSV) technology to enable an integrated system within a single package.
ATM Devices class and application environment:
- Class M for military(terrestrial and avionics) application .
- Class S for Space application .
ATM Devices include:
- Flip-chip 2.1D, 2.5D, 3D
- System In Package (SIP)
- Multi Chip Module (MCM)
For ATM devices with 2.1D/2.5D/3D packaging technology: Manufacturer(s) shall document in the PIDTP for multiple die integration and interconnection methodology with include following:
- Multiple die integration through organic/ceramic substate;
- Density of the Integration of homogenous/heterogeneous die through substrate;
- Advanced organic build-up substrate technology with fine lines and spaces;
- Interposers technology utilizing through silicon vias(TSV) or TGV (glass) or EMIB;
- Copper pillar and micro-bump flip chip interconnects;
- Ball/Bumps Grid Array second level interconnects;
- Stacked die with through silicon via interconnects;
- High density integration between and among die stacks
RHA test Challenges on stacked ATM devices :
- TID test on Stacked heterogenous die devices
- Example: Die 1( FRAM) and die 2 (Microcontroller) stacked with wire connected and both Die tested TID individually.
- Is ok to TID test individual die ?
- should TID test perform on unique device?
- Heavy ion SEE test on stacked die is not possible!!
- SEE test on individual die is acceptable ??
- If we know individual die RHA test characteristics , that might help design engineers to
know devices RHA data.
ATM devices testability :
- WE know all component of ATM devices except TSV/TGV
- Interconnections from QML stacked flip chip devices.
- Individual die wafer acceptance test
- Underfill characteristics.
- Bumps
- If used passive elements- know how to and test.
- Terminal , ball or CGA how to attach and test.
- All RHA characteristics to individual die.
- Screening test : wafer lot acceptance test, Thermal characteristics, burn-in , temperature cycling test, final electrical test and external visual inspection etc.
- QCI test : Group C life test : individual die or entire device (may be) Burn In life test; Group D package related test like mechanical Thermoshock/Vibration test, lead integrity if BGA/CGA , Die attach etc. RHA group E test: TID, SEE test etc.
Package manufacturing supply chain:
- Who is supplying multiple dies (i.e. memory dies , driver dies and GPU die) from which wafer fab?
- Interconnect technology TSVs/ TGVs reliability
- Silicon bridge (EMIB) reliability for interconnection between the HBM2 stack and the GPU for intel CoWoS.
- Flip chip underfill suppliers’ evaluation
- Micro bumps/interposes alignment on the substrate.
- Who is PCB manufacturers ?
- Radiation hardness assurance (RHA) test , such as total ionizing dose (TID) and heavy ion single event effects (SEE) test.
- Where is the devices package assembly facility and risk analysis?
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